1. Field of the Invention
This invention relates to interpolative PCM decoders, and more particularly to an interpolative PCM decoder which can be changed-over between A-law and .mu.-law uses.
2. Description of the Prior Art
An interpolative PCM decoder is described in detail in G. R. Ritchie et al; "Interpolative Digital to Analog Converters", IEEE, COM-22, 11, Nov. 1974.
The feature of this system resides in that all the quantization levels are not realized with a ladder circuit, but that only the ends of segments are realized with the ladder circuit, equally divided levels within the segments being realized by time-related averaging operations.
As will be stated in detail later, the interpolative PCM decoder disclosed in the above literature is for the .mu.-law. It cannot be used as an interpolative PCM decoder for the A-law, which needs to be constructed separately. Whether an interpolative PCM decoder is for the A-law or for the .mu.-law is decided, as will be stated later, depending on whether a logic circuit within the decoder is for the A-law or for the .mu.-law. Therefore, in order to use one interpolative PCM decoder for both the A-law and the .mu.-law, both a logic circuit for the .mu.-law and a logic circuit for the A-law must be included in the decoder, and approximately twice as many hardware elements as those for the .mu.-law use alone are required.